1. Field
The present disclosure relates to a method and apparatus for employing dynamic random access memory (DRAM) to implement static random access memory (SRAM) output operations.
2. Discussion of Related Technology
Dynamic random access memory (DRAM) is slower and much less expensive per storage cell than static random access memory (SRAM). In addition, because each storage cell is simple, DRAM has a much higher storage density than SRAM and is generally used as main memory in computers. On the contrary, SRAM is faster, but more expensive than DRAM and is generally used for speed-critical areas of the computer such as cache memory or buffer memory.
An advantage of DRAM is structural simplicity: only one transistor and capacitor are required per memory cell. This allows DRAM to reach very high densities at low cost. However, the disadvantage is that since each memory cell stores bit information by charging each cell storage capacitor to a desired voltage value, DRAM must be constantly refreshed.
Each memory cell in SRAM includes a pair of cross-coupled transistors and a pair of access transistors serving to control access to the memory cell during read and write operations. This increases circuit complexity and makes SRAM more expensive than DRAM. However, SRAM does not need to be periodically refreshed, thereby allowing a CPU or other units to access the SRAM without interrupt.
That is, DRAM must be periodically refreshed, thereby causing delay when accessed. Hence, when fast access to memory is critical, SRAM is used despite the disadvantages of SRAM in terms of degree of integration, cost, and power consumption.
In order to use DRAM to overcome the disadvantages of SRAM, a technology for employing a plurality of DRAM chips to implement SRAM output operations has been presented. More specifically, one of the DRAM chips is operated while others are refreshed, thereby effectively operating as SRAM through elimination of delay related to the refresh operation.
Korean Patent No. 10-0796179 discloses a method and system for masking DRAM refresh operations. Specifically, in order to prevent delay caused by refresh of DRAM during read and write operations and to replace conventional SRAM, two DRAM arrays are used, and circuits are added or modified on control and data paths of conventional DRAM and are provided on a semiconductor wafer. However, this technology is complicated and thus can only be implemented on the semiconductor wafer.
Japanese Patent Application Publication Nos. 2003-297082 and 2008-257742 disclose a technology of using two DRAM to replace SRAM. This technology can employ general chip- or die-type DRAM. However, since the two DRAM chips need to be independently controlled, the device is complicated in structure and an extra delay is needed in data processing. Besides, since two DRAM chips are independently operated, each of the DRAM chips needs a controller, a data bus and an address bus, thereby causing data mismatch between the two DRAM chips. In particular, an increased data width may increase device complexity, and a dedicated controller chip may be needed. In this case, it's unlikely that this technology will be applied to low volume production.
Since the aforementioned conventional technologies using two DRAM chips require a data bus and an address bus dedicated to each DRAM, circuit complexity is high and data mismatch occurs between the two DRAM chips. Hence, a variety of supplemental circuits are used to overcome these problems.
The discussion in this section is to provide general background information and does not constitute and admission of prior art.